1. Field of the Invention
The present invention relates to a gate bias circuit of a power amplifier FET. More particularly, it relates to such a gate bias circuit of a power amplifier FET, for maintaining a specific operating current, by a compensation of deviation of a threshold voltage among each device, caused by irregularity of production processing in GaAs FET for power amplification.
2. Discussion of Related Art
As shown in FIG. 1, a conventional gate bias circuit of a power amplifier FET includes a gate G of an FET 1, to which a bias voltage formed by dividing DC voltage VDD with a resistor R.sub.1 and a resistor R.sub.2 which are, in series, connected to each other, is applied, and an input terminal 2 connected through a condenser 3.
A drain D of the FET 1 is connected to an output terminal 7 via resistor 4, resistor 5 and condenser 6. A drain bias terminal 9 where a drain voltage V.sub.dd is connected, is connected to a connection point of the resistor 4 and resistor 5 via a choke coil 8 for blocking a high frequency, and simultaneously, is grounded via a condenser 10 for blocking a direct current.
A high frequency signal input to the input terminal 2 is transmitted to the gate G of FET 1 via the condenser 3, in the above-described gate bias circuit of a power amplifier FET.
A gate voltage of Vg=V.sub.DD R.sub.2 /R.sub.1 +R.sub.2, formed by dividing a DC voltage V.sub.DD which is applied to a gate bias terminal 12, with a resistor R.sub.1 and a resistor R.sub.2, is applied to the gate G of FET 1.
When the gate voltage Vg is applied and the drain voltage V.sub.dd is applied to the drain bias terminal 9, a drain current ID which is determined by DC characteristics of FET 1, the gate voltage Vg and the drain voltage V.sub.dd, gets to flow from the drain D to the source S.
By this, the high frequency signal applied to the gate G of FET 1 via the condenser 3, is amplified to output via the resistor 4, resistor 5, and condenser 6.
Regarding curve b in FIG. 2, the drain current ID is determined by a threshold voltage Vth, the gate voltage Vg and a gain coefficient K in accordance with the formula (1) given as follows; EQU ID=K(Vg-Vth).sup.2 (1)
When the threshold voltage Vth is constant, the drain current ID is determined by the gate voltage Vg, and an operating point Q is also determined, as depicted in FIG. 3. FET's output characteristics and efficiency, etc. vary with a position of operating point Q. In this regard, the operating point Q, i.e., an operating current Iop, is to be constant, to thereby obtain constant device characteristics.
However, the conventional gate bias circuit of power amplifier FET includes the constant DC voltage V.sub.DD which is applied to the gate bias terminal 12, fixed resistors R.sub.1 and R.sub.2 as well as the constant gate voltage of Vg=V.sub.DD R.sub.2 /R.sub.1 +R.sub.2 which is applied to the gate G of FET 1.
When the threshold voltage Vth changes, therefore, the drain current ID is also changed, as known by the formula (1).
That is to say, when the gate voltage Vg is constant and the threshold voltage Vth changes, based on the formula (1), ID varies with the quadratic function of the threshold voltage Vth, varies the curve a or c in FIG. 2 according to the increase and/or decrease of the threshold voltage Vth.
The operating point is, therefore, shifted from Q to Q.sub.1 or Q.sub.2, causing the operating current Iop to largely vary with the change of the threshold voltage Vth, as illustrated in FIG. 3.
In the meantime, the threshold voltage Vth of every product FET is not constant by environment and materials, during fabricating of FET.
Therefore, the conventional gate bias circuit of a power amplifier FET suffers the disadvantages, in that each of the products has different threshold voltages, causing the operating point Q, i.e., operating current Iop to be changed, thereby varying the output characteristics and efficiency of the FET.